The present invention relates to a synchronous DRAM controller for synchronously controlling the readout operation of a DRAM (Dynamic Random Access Memory).
A synchronous DRAM controller (hereinafter described as SDRAM controller) generates a readout clock signal (hereinafter described as SCLK) that controls the data readout operation of the synchronous DRAM (hereinafter described as SDRAM) from the system clock signal (hereinafter described as DCLK) which is a reference for its own control operation. This SCLK is delayed by Td1 in relation to the DCLK on the process of passing through the inside of the SDRAM controller and the printing wiring board on which the SDRAM controller is mounted. This delayed signal will be named as SCLK (1). The SCLK (1) is supplied to the SDRAM.
Further, the SDRAM controller, after receiving a read request from the internal bus, generates the address/data/control signal and supplies it to the SDRAM. When this occurs, the SDRAM takes in the read data only for one cycle of the SCLK (1) in synchronization with the SCLK (1). Along with this read data that has been taken in, the SDRAM outputs the SCLK (1). Thereafter, the read data is taken in at each cycle of this SCLK (1) and is outputted.
This read data is delayed by Td2 (Td1≈Td2) on the process of passing through the inside of the SDRAM controller and the printing wiring board on which the SDRAM controller is mounted. Similarly, the SCLK (1) outputted by the SDRAM is also delayed by Td2 (Td1≈Td2) on passing through the inside of the SDRAM controller and the printing wiring board on which the SDRAM is mounted. This signal will be named as SCLK (2). The read data is transferred to the SDRAM controller in synchronization with the SCLK (2). Further the clock conversion of SCLK (2) to DCLK is executed. The SDRAM controller, after transferring the read request to the SDRAM, sends a data signal to the internal bus, assuming that a predetermined read data has been received after a predetermined clock cycle.
However, the conventional technique had the following problem to be solved.
That is, the SCLK (2) is delayed by Td1+Td2 in relation to the DCLK as mentioned above. Therefore, there occurred a problem such that, when the SDRAM controller received the read data and SCLK (2) from the SDRAM, the read data that could have been determined to fall within a cycle of adjacent pulses of SCLK (2) could not be determined to fall within the cycle, just the moment the clock signal SCLK (2) was converted into DCLK.
In order to solve this situation, there was a need to shorten the delay time of SCLK (2) in relation to DCLK, or to extend the cycle of the clock signal. As a result, sophistication of the inner layout of an LSI in order to shorten the delay time, or lowering the frequency of DCLK in order to extend the cycle of the clock signal was required for the measure.
In the synchronous DRAM controller relating to the present invention, when receiving a read request to the SDRAM (Synchronous Dynamic Random Access Memory) from an internal bus, a control sequencer outputs a start readout signal that synchronizes with the system clock. A start readout operation unit starts transferring a readout clock signal to the SDRAM, when receiving the start readout signal from the control sequencer. A signal delay path receives the readout clock signal from the start readout operation unit, delays the signal to transfer it to the SDRAM, and further delays a part of the readout clock signal to transfer it to the control sequencer. A temporary read data retention unit receives and temporarily retains a read data outputted by the SDRAM at each cycle of the readout clock signal through the signal delay path. When receiving a part of the readout clock signal from the signal delay path, the control sequencer sends a read data storage enabling signal to the temporary read data retention unit, makes the temporary read data retention unit temporarily retain the read data taken in to be synchronized with the readout clock signal, and outputs a read data readout enabling signal in order to output the read data to synchronize with the system clock signal.
By realizing such configuration, a read data taken in from the SDRAM in accordance with each cycle of the readout clock signal, which is delayed by a predetermined time in the signal delay path, is temporarily stored in the temporary read data retention unit in accordance with a timing of the readout clock signal traveling through the same path, having a delay of the same period of time. In this manner, the read data has been retained accurately before the control sequencer sends the read data readout enabling signal synchronized with the system clock. Thus, it is possible to prevent indeterminacy of the read data taken in at each cycle of the readout clock signal.